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NX2415
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH INTEGRATED FET DRIVER AND DIFFERENTIAL CURRENT SENSE
PRELIMINARY DATA SHEET Pb Free Product The NX2415 is a two-phase PWM controller with inte- n Differential inductor DCR sensing eliminates the problem with layout parasitic grated FET driver designed for low voltage high current n External programmable voltage droop application. The two phase synchronous buck converter offers ripple cancelation for both input and output. The n Low Impedance On-board Drivers NX2415 uses differential remote sensing using either n Hiccup current limit current sense resistor or inductor DCR sensing to achieve n Power Good for power sequencing accurate current matching between the two channels. n Enable Signal allows external shutdown as well as programming the BUS voltage start up threshold Differential sensing eliminates the error caused by PCB n Programmable frequency board trace resistance that is otherwise is present when using a single ended voltage sensing. In addition the n Prebias start up NX2415 offers high drive current capability especially for n Over voltage protection without negative spike at output keeping the synchronous MOSFET off during SW node n Pb-free and RoHS compliant transition, accurate programmable droop allowing to reduce number of output capacitors, accurate enable circuit provides programmable start up point for Bus volt- n Graphic card High Current Vcore Supply age, PGOOD output, programmable switching frequency n High Current +40A on board DC to DC converter and hiccup current limiting circuitry. applications
10
31
1uF 23 1uF 24 25 26 22 21 620 0.22uF 2.15 M1 0.68uH
DESCRIPTION
FEATURES
APPLICATIONS
TYPICAL APPLICATION
+5V
10k 6.49k VCC EN
PVCC1
+5V
2 x 10uF
1uH
30
BST1 HDRV1
VIN1 +12V
100uF
180uF
+12V
1.65k op 45.3k 10k
29 7 2 28 11
ENBUS DROOP
SW1 LDRV1
VOUT +1.2V/50A
2 x (1000uF,7mohm ESR)
M2
620 1uF
+5V
NX2415
RT PGOOD CSCOMP
PGND1
CS+1 9 CS-1 10 PVCC2 18 1uF 17 16 15 19 20 620 0.22uF 2.15 M3 0.68uH
VOUT
430
220nF 2.2nF
+5V
10uF
3 PGSEN
1nF
10k 20k 1.8nF 3.92k 5.62k 10k 2N3906 1k 180k 10nF 1nF 20k
BST2 HDRV2 SW2 LDRV2
6.8nF
5 FB 6 VCOMP
150pF 10nF 100k
M4
620 1uF
4 VP 8 OCP 1 VREF 14
PGND2
12 CS+2 CS-2 13
IOUT
AGND 32
Figure1 - Typical application of NX2415
ORDERING INFORMATION
Device NX2415CMTR
Rev.4.8 05/06/08
Temperature 0 to 70oC
Package MLPQ-32L
Frequency 200kHz to 1MHz
Pb-Free Yes 1
NX2415
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 6.5V BST to PGND Voltage ...................................... -0.3V to 35V SW to PGND .................................................... -2V to 35V All other pins .................................................... -0.3V to 6.5V Storage Temperature Range ............................... -65oC To 150oC Operating Junction Temperature Range ............... -40oC To 125oC Lead temperature(Soldering 5s) ........................... 260oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
32-LEAD PLASTIC MLPQ 5 x 5
PGOOD ENBUS VCC SW1 NC EN HDRV1 24 BST1 23 PVCC1 22 LDRV1 AGND VREF RT PGSEN VP FB COMP DROOP OCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS-1 CSCOMP HDRV2 CS+1 IOUT CS-2 CS+2 SW2
32 31 30 29 28 27 26 25
NX2415
21 PGnd1 20 PGnd2 19 LDRV2 18 PVCC2 17 BST2
JA 35o C /W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, V BST-VSW =5V, EN=HIGH, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETER Supply Voltage(Vcc) VCC ,PVCC Voltage Range VCC Supply Current (static) PVCC Supply Current (Dynamic) VBST Voltage Range VBST Supply Current ((Dynamic))
SYM VCC
TEST CONDITION
MIN 4.5 -
TYP 5 6.6 4
MAX 5.5
UNITS V mA mA
ICC (Static) EN=LOW EN&ENBUS HIGH, ICC Freq=200Khz per phase (Dynamic) CLOAD=2200PF VBST to VSW EN&ENBUS HIGH, VBST Freq=200Khz per phase (Dynamic) CLOAD=2200PF
4.5
5 4
5.5
V mA
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NX2415
PARAMETER Under Voltage, Vcc , Enable(EN) & ENBUS VCC-Threshold VCC-Hysteresis EN Threshold EN Hysteresis ENBUS Threshold ENBUS Hysteresis Reference Voltage Ref Voltage Ref Voltage line regulation Oscillator (Rt) Frequency for each phase Ramp-Amplitude Voltage Ramp Peak Ramp Valley Max Duty Cycle Min Duty Cycle Transconductance Amplifiers(CSCOMP) Open Loop Gain Transconductance Voltage Mode Error Amplifier Open Loop Gain Input Offset Voltage Output Current Source Output Current Sink Output HI Voltage Output LOW Voltage SS (Internal ) Soft Start time Power Good(Pgood) Threshold Hysteresis PGood Voltage Low High Side Driver(CL=4700pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Rsource(Hdrv) Rsink(Hdrv) THdrv(Rise) THdrv(Fall) I=200mA I=200mA VBST-VSW=4.5V VBST-VSW=4.5V 1.1 0.8 24 24 30 ohm ohm ns ns ns Vio_v 5 5 Vcc-1.5 0.5 Tss 200Khz/Phase VSEN Falling IPGood=-5mA 20 74 5 0.5 SYM TEST CONDITION MIN TYP MAX UNITS
VCC_UVLO VCC_Hyst
VCC Rising Vcc Rising VBUS Rising
4 0.2 0.6 0.1 1.6 0.16 0.8 1
V V V V V V V % KHz V V V % %
VREF
4.5VFs VRAMP
Rt=45kohm
400 1 2.5 1.5 95 0
200Khz/Phase
50
65 1600
dB umoh
50 0
dB mV mA mA V V mS %VID % V
Tdead(L to Ldrv going Low to Hdrv going H) High, 10%-10%
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NX2415
PARAMETER Low Side Driver (CL=4700pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time Current Sense Amplifier(CS+, CS-) Current Sense Amplifier Mismatch Voltage Gain Droop Voltage Current Source(Droop) Droop Voltage Current Source SYM TEST CONDITION MIN TYP MAX UNITS
Rsource(Ldrv) Rsink(Ldrv)
I=200mA I=200mA
1.1 0.5 40 36 30
ohm ohm ns ns ns
TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10%
0 K 29.7 30 30.3
mV V/V
V(IOUT)=0.6V,feedback resistor=10kohm,Rdroop=60 kohm 200Khz/Phase
100
uA
OCP Adjust Blank time before activating OCP Vref Reference Voltage Driving current ability OVP Threshold OVP Threshold
15
uS
1.6 5 0.96
V mA V
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NX2415
PIN DESCRIPTIONS
PIN # 31 SYMBOL VCC PIN DESCRIPTION IC's supply voltage. This pin biases the internal logic circuits. A minimum 1uF ceramic capacitor is recommended to connect from this pin to ground plane. High side gate driver outputs.
25, 16 22, 19 30
HDRV1, HDRV2 LDRV1, LDRV2 EN
Low side gate driver outputs.
This pin is used to remotely turn off the controller. The pin has a threshold voltage of 0.6 volts.
24, 17 26,15 23, 18 28
BST1,BST2 These pins supplies voltage to high side FET drivers. SW1,SW2 PVCC1, PVCC2 PGOOD These pins are connected to the source pins of the upper fets. These pins provide the supply voltage for the lower MOSFET drivers.
This pin is an open collector output. If used, it should be pulled to 5V with a resistor greater than or equal to 10k, otherwise it my be left open. Any fault or under voltage on the enable pins will cause the signal to be pulled low. Input to the positive pin of the error amplifier. A resistor is connected from the output of the DAC to this pin. Place a small capacitor from this pin to GND to filter any noise. This pin is the error amplifier inverting input. It is connected to the output voltage via a voltage divider. This pin programs the internal oscillator frequency using a resistor from this pin to ground. The frequency of each phase is 1/2 of this frequency.
4
VP
5
FB
2
RT
9,12
CS+1,CS+2 Positive input of the differential current sense amplifiers. It is connected directly to the RC junction of the respective phase's output inductor. CS-1,CS-2 Negative input of the differential current sense amplifiers. It is connected directly to the negative side of the respective phase's output inductor. The output of the transconductance op amp for current balance circuit. An external RC is connected from this pin to GND to stabilize the current loop. This is the output pin of the error amplifier. The compensation network connection.
10,13
11
CSCOMP
6
VCOMP
7
DROOP
A resistor from this pin to ground programs an internal current source that is fed into the FB pin. This current source is proportional to the output current of the regulator. The product of this current times the external resistor RFB provides a droop voltage.
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NX2415
PIN # 8 SYMBOL OCP PIN DESCRIPTION A resistor divider connected from this pin to Vref programs the current limit threshold. The outputs of the internal current sense differential amplifiers are summed together to represent the output current. This voltage is then compared to this threshold. A 1.6V buffered reference is brought out. This pin is used to program the under voltage lockout of the bus supply. A resistor divider from the bus voltage to this pin programs the under voltage lockout. When the voltage of this pin is greater than 1.6V, the bus voltage is assumed in operation. The pin has a 10% hysterisis. This is the ground connection for the power stage of the controller.
1 29
VREF ENBUS
21, 20 32 14
PGND1, PGND2 AGND IOUT
Controller analog ground pin. Input of OCP amplifier. Place a 10nF to 100nF capacitor from this pin to GND to filter any noise. Output over voltage and Pgood sensing pin. A resistor divider plus a small capacitor should be connected to the this pin to set the OVP and Pgood.
3
PGSEN
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NX2415
BLOCK DIAGRAM
VCC Bias generator 0.8V 1.6V 1.25V Enbus 1.6/1.44 EN 0.64 /0.53V Vp Digital start FET driver 0.8V SS_finish Dis_EA FB
OVP
UVLO
UVLO
PVCC1 PVCC2 BST1
Hiccup
start BST2 DrvH1 DrvH2 DrvL2 DrvL1
SW1 SW2
R S
Droop current ramp1 Two phase OSC set2 ramp2
PGND1
Q
PGND2
VCOMP Rt
Set1 K=30 KR V1.25 R KR CS+1 CS-1 R PWM control logic and driver KR V1.25 R CS+2 CS-2
CS01 CS02
Vref
1.6V
0.8*120% OVP
R KR Slave channel control CScomp
PGsen
V1.25
0.64/0.6 SS_finished Hiccup 32 cycles filter Hiccup Logic
6 Cycles filter Current Mirror
/ 2
gm*Ri=0.6
gm IOUT Ri OCP
Pgood
AGND
Droop
FB
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NX2415
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS - Input voltage - Output voltage - Output current - Operation frequency for each channel
L OUT =0.54uH
Choose inductor from Vishay IHLP_5050FD-01 with L=0.68uH DCR=1.4m. Current Ripple is recalculated as
DVRIPPLE - Output voltage ripple DIRIPPLE - Inductor current ripple
IRIPPLE = =
VIN -VOUT VOUT 1 x x LOUT VIN FS
...(2) 12V-1.2V 1.2V 1 x x = 3.97A 0.68uH 12V 400kHz
Design Example
The following is typical application for NX2415. VIN = 12V VOUT=1.2V IOUT=50A IOUT_max=60A DVRIPPLE <=12mV DVDROOP<=120mV @30A step FS=400kHz Phase number N=2
Output Capacitor Selection
Output capacitor value is basically decided by the output voltage ripple, capacitor RMS current rating and load transient. Based on Voltage Ripple For electrolytic, POSCAP bulk capacitor, the ESR (equivalent series resistance) and inductor current typically determines the output voltage ripple.
ESRdesire =
VRIPPLE 12mV = = 3.022m IRIPPLE 3.97A
...(3)
If low ESR is required, for most applications, mul-
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
tiple capacitors in parallel are better than a big capacitor. For example, for 12mV output ripple, SANYO OSCON capacitors 2R5SEPC1000MX(1000uF 7m) are chosen.
N=
E S R E x IR I P P L E VR IPPLE
...(4)
Number of Capacitor is calculated as
L OUT =
VIN -VOUT VOUT 1 x x IRIPPLE VIN FS IOUTPUT N
...(1)
7m x 3.97A 12mV N =2.3 For ceramic capacitor, the current ripple is determined by the number of capacitor instead of ESR N=
COUT = IRIPPLE 8 x FS x VRIPPLE
...(5)
IRIPPLE =k x
where k is between 0.2 to 0.4. Select k=0.2, then
12V-1.2V 1.2V 1 L OUT = x x 50A 12V 400kHz 0.2 x 2
Typically, the calculated capacitance is so small that the output voltage droop during the transient can not meet the spec although ripple is small.
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NX2415
Based On Transient Requirement Typically, the output voltage droop during transient is specified as:
VDROOP ...(6)
0 if LEFF Lcrit = LEFF x Istep - ESR E x CE V OUT
if LEFF Lcrit
...(10)
For example, assume voltage droop during transient is 120mV for 30A load step. If the OS-CON capacitors (1000uF, 7m ) is used, the critical inductance is given as
Lcrit =
ESR E x C E x VOUT = Istep
7m x 1000F x 1.2V = 0.28H 30A
The effective inductor value is 0.34uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
where is the a function of capacitor, etc.
0 if LEFF Lcrit = LEFF xIstep - ESR x COUT V OUT
where
if LEFF Lcrit
...(7)
number of capacitors is
= =
...(8)
LEFF x Istep VOUT
- ESR E x CE
L EFF = L crit
LOUT 0.68uH = = 0.34uH N 2 ESR x COUT x VOUT ESR E x C E x VOUT = = Istep Istep
0.34H x 30A - 7m x 1000F = 1.5us 1.2V
ESR E xIstep Vtran + VOUT x2 2 x LEFF x CE xVtran
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
N= =
7mx 30A + 120mV 1.2V x (1.5us)2 2 x 0.34Hx1000F x120mV = 1.78
The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2. It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. 9
...(9)
where
Rev.4.8 05/06/08
NX2415
Control Loop Compensator Design
NX2415 can control and drive two channel synchro-
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 2 x x R4 x C1 x C2 C1 + C2
...(11) ...(12) ...(13) ...(14)
nous bucks wih 180o phase shift between each other. t
One of two channels is called master, the other is called slave. They are connected together by sharing the same output capacitors. Voltage loop is designed to regulate output voltage. In order to achieve the current balance in these two synchronous buck converters, current loop compensation network is employed to to make sure the currents in slave is following the master.
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
Voltage Loop Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response,compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50 and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. A. Type III compensator design For low ESR output capacitors, typically such as Sanyo OSCON and POSCAP, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. In design example, six electrolytic capacitors are used as output capacitors. The system is compensated with type III compensator. The following figures and equations show how to realize the this type III compensator with electrolytic capacitors.
o
the compensator.
Zin R3
Vout
Zf C1 C2 R4
R2 C3 R1
Fb Ve Vref
Figure 2 - Type III compensator
Gain(db)
power stage FLC
40dB/decade
loop gain
FESR
20dB/decade
compensator
FZ1 FZ2 FP1
FO FP2
Figure 3 - Bode plot of Type III compensator
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NX2415
The transfer function of type III compensator is given by: 6. Calculate R4 by choosing FO=40kHz.
Ve VOUT
(1+ sR4 x C2 ) x [1+ s(R2 + R3 ) x C3 ] 1 = x sR2 x (C2 + C1) (1+ sR x C2 x C1 ) x 1+ sR x C ( 4 3 3) C2 + C1
Use the same power stage requirement as demo
R4 = =
VOSC 2 x x FO x LEFF R2 x R3 x x Vin ESR R2 + R3
1V 2 x x 40kHz x 0.34uH 10k x 3.92k x x 12V 3.5m 10k + 3.92k =5.73k
Choose R4=5.62k. 7. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
board. The crossover frequency has to be selected as FLCC2 = =
1 2 x x FZ1 x R 4
FLC = =
1 2 x x LEFF x COUT 1
1 2 x x 0.75 x 6.1kHz x 5.62k = 6.2nF
2 x x 0.34uH x 2000uF = 6.1kHz
Choose C2=6.8nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency.
FESR
1 = 2 x x ESR x COUT 1 2 x x 3.5m x 2000uF = 22.7kHz =
C1 = =
1 2 x x R 4 x FP2
2.Set R2 equal to10k.
1 2 x x 5.62k x 200kHz = 141pF
Choose C1=150pF. B. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure 4. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.
R x VREF 10k x 0.8V R1= 2 = = 20k VOUT -VREF 1.2V-0.8V
Choose R1= 20k. 3. Calculate C3 by setting FZ2 = FLC and Fp1 =FESR.
1 1 1 C3 = ) x( 2 x x R2 Fz2 Fp1 1 1 1 = ) x( 2 x x 10k 6.1kHz 22.7kHz =1.9nF
Choose C3=1.8nF. 5. Calculate R 3 by equation (13).
R3 = =
1 2 x x FP1 x C3
Gain= Fz =
1 2 x x 22.7kHz x 1.8nF = 3.89k
Choose R3=3.92k.
R3 R2
... (15) ... (16) ... (17)
1 2 x x R3 x C1 1 2 x x R 3 x C2
Fp
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NX2415
FLC = 1 2 xx LEFF x COUT 1
C2 Vout R2 Fb Ve R1 Vref
FESR = =
R3
C1
=
2 xx 0.75uHx10800uF = 1.768kHz
1 2 x x ESR x COUT
Figure 4 - Type II compensator
1 2 x x 13m x 1800uF = 6.801kHz
2.Set R2 equal to10k and calculate R1.
R1=
power stage Gain(db) 40dB/decade loop gain 20dB/decade
R 2 x VREF 10k x 0.8V = = 20k VOUT -VREF 1.2V-0.8V
3. Set crossover frequency FO=15kHz. 4.Calculate R3 value by the following equation.
R3= =
V O S C 2 x x FO x L E F F x x R2 V in ESR
1V 2 x x 15kHz x 0.75uH x x 10k 12V 2.16m =27.3k
Choose R 3 =27.4k. 5. Calculate C1 by setting compensator zero FZ
compensator Gain
at 75% of the LC double pole.
C1= 1 2 x x R3 x Fz
FZ FLC FESR FO FP
Figure 5 - Bode plot of Type II compensator For this type of compensator, FO has to satisfy FLC=
1 2 x x 27.4k x 0.75 x 1.768kHz =4.4nF
Choose C1=4.7nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency.
C2= = 1 x R 3 x Fs
1 x 2 7 .4k x 1 0 0 k H z =116pF
Choose C2=100pF.
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NX2415
Current Loop Compensator Design
Power stage Master channel Compensation D(s) 1 Vosc d Vin s*L+Req iL
Current Sensing Amplifier Gain
s*L+DCR Rs*Cs*s+1 Inductor Current sense
Figure 6 - Current loop control diagram
VIN
master channel DCR L
Vbias
Rs Rs VIN PWM control logic and driver
Cs VOUT
Slave channel 1 DCR L
Ramp for slave channel Vbias
Rs Rs Icomp1 Rcc C1
Cs
Slave channel control C2 Slave channel control Slave channel
Figure 7 - Function diagram of current loop
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NX2415
Inductor Current Sensing
VIN iL Control & Driver L DCR VOUT Rs Current Sensing Amplifier Cs VS_IL
racy during the transient if droop function is required. The illustration is shown in the following figure.
VS_IL----Voltage accross the sensing capacitor Cs iL--- inductor current
Overshoot caused by inductor nonlinearity
Rs
Figure 8 - Inductor current sensing using RC network. The inductor current can be sensed through a RC network as shown above. The advantage of the RC network is the lossless comparing with a resistor in series with output inductor. The selection of the resistor sensing network is chosen by the following equation:
R S x CS = L DCR
Droop misbehavoir caused by overshoot of VS_IL Output voltage with droop function
...(18)
Figure 9 - Droop accuracy affected by the nonlinearity of inductor. In this case, the sensing resistor has to be chosen
If the above equation is satisfied, the voltage across the sensing capacitor Cs will be equal to the inductor current times DCR of inductor for all frequency domain.
VS _ IL = DCR x iL
RS
L DCR x CS
to compensate the overshoot. This selection only affects the small signal mode of current loop. For DC accuracy, there is no effect since the DC voltage across the sensing capacitor will equal to the DCR times inductor current at DC load no matter what Rs is. In this example, Rs=620. RS value is preferred to be less than 400 in NX2415's application, therefore we need to reiterate the calculation, choose CS 2.2uF instead. RS value is finally chosen as 301 . Powe dissipation of Rs resistor is calculated as followed:
If the sensing capacitor is chosen
CS = 1F CS must be X7R or COG ceramic capacitor. The sensing resistor is calculated as RS = L DCR x CS
For example, for 0.68uH inductor with 1.4m DCR, we have
RS =
0.68H = 486 1.4m x 1F
In most of cases, the selection of sensing resistor based on the above equation will be sufficient. However, for some inductor such as toroid coiled inductor with micrometal, even the product of sensing resistor and capacitor is perfectly match with L/DCR, the voltage across the capacitor still has overshoot due to the nonlinearity of inductor. This will affect the droop accu-
PD (RS ) = =
(VIN - VOUT )2 V2 x D + OUT x (1 - D) RS RS
(12 V - 1.2V)2 (1.2 V)2 x 0. 1 + x (1 - 0.1) 301 301 = 0.04 W
The power rating of Rs should be over 0.04W.
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NX2415
Current Loop Compensation
FP1 =
Slave channel power stage
Req 2x xL
=
7.4m = 1.7kHz 2 x x 0.68H
The current compensation transfer function is
-20 dB
given as
D(s) = gm x s x ( C1 + C2 ) 1 + s x Rcc x C1 R x C1 x C2 1 + s x cc C1 + C2
Current loop compensation
It has one zero and one pole. The ideal is to
Loop gain for slave channel -20dB 0 DB -40dB Fzc Fo Fpc
choose resistor Rcc to achieve desired loop gain such as 50kHz. Rcc can be calculated as
Fp1
Rcc =
where
2 x x Fo x L x Vosc gm x VIN x K C x DCR 60 k = 22.9 2k+ RS
...(19)
Figure 10 - Bode plot of current loop The diagram and bode plot for current loop of NX2415 is shown in above figures. The current signal through inductor sensing is amplified by current sensing differential amplifier. The amplified slave current signal is compared with the amplified inductor current from master channel (channel 1 for NX2415) through a transconductance amplifier, the difference between channel current will change the output of transconductance amplifier, which will compare with a internal ramp signal and changes the duty cycle of slave channel buck converter. If the inductor are perfectly matched and the PWM controller has no offset, the DC current in slave channel will equal to the DC current of master channel (channel 1) due to the gain of current loop. From the bode plot, the power stage has one pole located at
KC
60k and 2k is the internal resistance for the current sensing amplifier. For fast response, we can set the current loop cross-over frequency one and half times of voltage loop cross-over frequency. Since the voltage loop cross-over frequency is typically selected as 1/10 of switching frequency, we choose FO=50kHz.
Rcc = 2 x x 50kHz x 0.68H x 1V = 442 1.6mA / V x 12 V x 22.9 x1.4m
Select
Rcc = 430 .
The selection of capacitor C1 is such that the zero of compensation will cancel the pole of power stage, therefore,
C1 = L 0.68H = = 214nF Req x Rcc 7.4m x 430
2xxL where Req is the equivalent resistor and it is given by
R eq DCR + R dson _ con x VOUT V + Rdson _ syn x 1 - OUT VIN VIN
FP1 =
Req
Typically, the capacitor C1 is so big that the current loop may start slowly during the start up. Therefore, smaller capacitor can be selected. However, the selected capacitor can not reduce too much to cause phase droop. Select C1=220nF. The capacitor C2 is an option and it is used to filter out the switching noise. C2 can be calculated as
R dson _ con is the Rdson of control FET and R dson _ syn is
the Rdson of synchronous FET. For this example,
Req = 7.4m
The pole is located as
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VREF
1 1 C2 = = = 1.85nF x Rcc x FS x 430 x 400kHz
Select C2=2.2nF.
100k
OCP
Frequency Selection
The frequency can be set by external Rt resistor. The relationship between frequency per phase and RT pin is shown as follows.
ROCP
Figure 12 - Over current protection
RT
18600000 FS
Output Voltage Droop Operation
...(20) The effective output impedance of the controller must be adjusted to maximize the output voltage fluctuation range. A program resistor attached to the Droop pin RDROOP will program this value. The function works by an internal current source connected to the FB pin. This current flows output of the FB pin and through the Rin resistance from the FB pin to the output. This current source is a function of the sensed output current. As the output current increases, the droop current will increase and causes the output voltage todroop proportionately. The droop current is programmed by a resistor attached to the Droop pin. The value of the resistor is chosen as follows.
FREQUENCY(kHz) vs RT(kohm )
800 700 600
frequency(kHz)
500 400 300 200 100 0 0 50 100 150 200
R t(kohm )
Figure 11 - Frequency vs Rt chart
Over Current/Short Circuit Protection
The converter will go into hiccup mode if the output current reaches a programmed limit V OCP determined by the voltage at pin OCP.
VOUT
RIN
FB VP
IDROOP
COMP
Error Amplifer
Figure 13 - Output voltage droop funciton
VOCP = 0.6 ROCP =
60k DCR IOCP 2k + R S 2
...(21)
VOUT = IDROOP x RIN = ILOAD x RLL
if we want Vout droops 60mV @ 20A,
RLL = 60mV = 3m 20A
...(22)
VOCP x 100k VREF - VOCP
Where RLL is desired load impedance. For example,
Where Iocp is the desired over current protection level,100k is the resistor connecting VREF pin and IOCP pin. RS is the current sensing matching resistor when using DCR sensing method.
IDROOP =
V(IOUT) RDROOP 60k DCR x x ILOAD 2k + RS 2 RDROOP
...(23)
0.6 x =
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Combine equation 22 and 23, be calculated. From this figure, it is obvious that a multiphase converter can have a much smaller input RMS ...(24) current, which results in a lower amount of input capacitors that are required. For example, Vin=12V, Vout=1.2V. The duty cycle is D=Vout/Vin=1.2/12=10%. From the figure, for two phase, the normlized RMS current is 0.2*Iout=0.2*50A=10A. A combination of ceramic and electrolytic(SANYO WG or WF series) or OSCON type capacitors can achieve both ripple current capability together with having enough capacitance such that input voltage will not sag too much. In this application, one OSCON SVPC180M(180uF, 16V, 2.8A) and three 10uF(4A rms current, X5R) ceramic capacitors are selected. A 1uH input inductor is recommended to slow down the input current transient. Suppose power stage efficiency is 0.8, then input current can estimated by
RDROOP =
0.6 60k DCRILOADRIN 2 2k + RS VOUT
Where DCR is the sense resistor or the DCR of the output inductor. RS is the current sensing matching resistor when using DCR sensing method. ILOAD is the load current. RIN is the input DC resistor of the master phase compensator which connect FB pin and PGSEN pin. For example, to have the DVOUT=60mV when the load current is 20A, DCR is 1.4m, RIN is 10k, RS is 620.
RDROOP = 32k
0.6 60k 1.4m x 20A x 10k = x x 2 2k + 0.62k 60mV
Choose RDROOP= 32k.
Over Voltage Protection
Over voltage protection is achieved by sensing the output voltage through resistor divider. The sensed voltage on PGSEN pin is compared with 120%*0.8V to generate the OVP signal. A small value capacitor is required to connect to PGSEN pin also.
VOUT 1.2V 10k
PGSEN 0.8V*120% OVP
IINPUT =
IO U T x VOUT 60 A x 1 . 2 V = = 7 .5 A 0 . 8 x 12 V x VIN
In this application, Coilcraft DO3316P_102HC with RMS rating 10A is chosen.
0.5 0.4
Singlephase Two phase
20k
1nF
I RMS (IN ) 0.3 Iout
0.2 0.1 0
Figure 14 - Over voltage protection
Three phase
0 0.1 0.2 D 0.3 0.4 0.5
Input Filter Selection
The selection criteria of input capacitor are voltage rating and the RMS current rating. For conservative consideration, the capacitor voltage rating should be 1.5 times higher than the maximum input voltage. The RMS current rating of the input capacitor for multi-phase converter can be estimated from the above Figure 15. First, determine the duty cycle of the converter (VO/ VIN). The ratio of input RMS current over output current can be obtained. Then the total input RMS current can
Figure 15 - Normalized input RMS current vs. duty cycle.
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Power MOSFETs Selection
The NX2415 requires two N-Channel power MOSFETs for each channels. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, eight NTD60N02 are used. They have the following parameters: VDS=25V, ID =62A,RDSON =12m,QGATE =9nC. There are three factors causing the MOSFET power loss:conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as:
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
Soft Start and Enable Signal Operation
The NX2415 will start operation only after Vcc and PVcc have reached their threshold voltages and EN and ENBUS have been enabled. The ENBUS pin can be programmed to turn on the converter at any input voltage. The ENBUS pin has a threshold voltage of 1.6V. Once the converter starts, there is a soft start sequence of 4082 steps between 0 and Vp. The ramp rate is determined by the switching frequency.
dVO VO = ...(27) dt 4082 x FS The softstart time is calculated as followed:
Tstartup = 4082 FS
...(28)
Layout Considerations
...(24) The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is ...(25) generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the ...(26) high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close
where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as:
PHCON =IOUT x D x RDS(ON) x K
2
PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
Where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency and should be selected for the worst case. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. 1 PSW = x VIN x IOUT x TSW x FS 2
TSW is the sum of TR and TF which can be found in
mosfet datasheet, IOUT is output current, and FS is switching frequency. Swithing loss PSW is frequency dependent.
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as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. 12. Inductor current sense line should be connected directly to the inductor solder pad.
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MLPQ 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
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MLPQ 32 PIN 5 x 5 TAPE AND REEL INFORMATION
NOTE: 1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL. 2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
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